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Preliminary
Product Description
The Sirenza Microdevices' SLX-2143 is a low noise amplifier module operating in the 1700 - 2200 MHz frequency band. This device has been optimized to serve high linearity base station applications where a high intercept point is required with low noise figure. The SLX-2143 uses PHEMT device technology, internal bias circuitry, and proven ceramic module technology to yield a high performance product with proven reliability. Internal RF matching is also included on both the input and output to provide an easy to implement, unconditionally stable, 50 ohm circuit block.
SLX-2143
1700-2200 MHz High Linearity Low Noise Amplifier Module
Noise Figure Noise Figure
2.00 1.75 Noise Figure (dB) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 1.5
Product Features
* * * * *
1.7 1.9 2.1 2.3 2.5
Very Low Noise Figure, 1.05dB High OIP3 = +35dBm at 2GHz Gain = 15dB, Low Gain Slope 50 Input/Output Match, Stable Single Supply Operation, Self Biased
Applications
*
Unit GHz dB dB dB dB dBm dBm ns
PCS, TDMA, CDMA, WCDMA receivers
Frequency (GHz)
Product Specifications
Symbol FO S21 S11 S22 NF OIP3 P1dB GD Frequency Range Gain Input Return Loss Output Return Loss Noise Figure Output Third Order Intercept Point Compression Point Group Delay Deviation from Linear Phase (over 100MHz) S12 Vdd Idd Rth Reverse Isolation Supply Voltage Supply Current Thermal Resistance (junction-back) Parameters Min. 1.7 13.5 10 10 - 32 15 12 13 1.05 34 20 <0.5 <0.15 -23 4.75 90 5 108 80 5.25 120 Typ. Max. 2.0 16.5 - - 1.3 - Min. >2.0 13 10 10 - 33 14.5 12 13 1.05 35 19 <0.5 <0.1 -23 Typ. Max. 2.2 16 - - 1.3 -
degrees dB V mA C/W
All parameters measured in a 50 ohm system, Vdd=5V, T=25C. OIP3 measured at a power of 6dBm per tone, 6MHz tone spacing. NOTE: For applications between 2.2 - 2.5GHz please contact apps@sirenza.com
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
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Preliminary
Absolute Maximum Ratings
Parameters Supply Current (Idd) Device Voltage (Vdd) Operating Temperature Storage Temperature Range Peak Reflow Temperature (30sec) Operating Junction Temperature Maximum Input Power Value 150 5.5 -40 to +85 -65 to +150 +230 +150 +20 Unit mA V C C C C dBm
Subjecting this device at or beyond any one of these limits may cause permanent damage. For reliable operation, the device operating voltage and current must not exceed the maximum values shown in the "Product Specifications" table. Bias conditions should also satisfy the following expression: VDD IDD RTH < TJ - TOP, where TJ is the junction temperature (150C) and TOP is the board temperature.
Gain
20 -40C 18 Gain (dB) 16 14 12 10 1.0 1.5 2.0 Frequency (GHz) 2.5 3.0 +85C
S12 (dB)
Input Return Loss
0 -40C -5 S11 (dB) -10 -15 -20 -25 1.0 1.5 2.0 Frequency (GHz) 2.5 3.0 +85C
S22 (dB) -5 -10 -15 -20 -25 1.0 1.5 -40C +85C 0
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Reverse Isolation
-10 -40C -14 -18 -22 -26 -30 1.0 1.5 2.0 Frequency (GHz) 2.5 3.0 +85C
Output Return Loss
2.0 Frequency (GHz)
2.5
3.0
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Preliminary
Noise Figure
2.00 -40C Noise Figure (dB) 1.50 +85C +35C
Output Intercept (dBm)
1.00
0.50
0.00 1.5 1.7 1.9 2.1 2.3 2.5
Frequency (GHz)
Compression Point P1dB @ 2GHz, +25C, Vdd=5
25 23 P1dB (dBm) 21 19 17 15 1.5 1.7 1.9 2.1 2.3 2.5 Frequency (GHz)
IP3 (dBm), P1dB (dBm), Gain (dB),NF (dBX10) 40
Group Delay, Devation from Linear Phase over 100MHz
Delay (nS), Deviation from Lin Phase (degs) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 1.7 1.9 2.1 2.3 2.5 100 3.0 3.3 Idd (mA) 105 Delay Dev. Linear Phase 107.5 110
Frequency (GHz)
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Output Intercept, OIP3
40 -40 38 36 34 32 30 1.5 1.7 1.9 2.1 2.3 2.5 +85C +35C Frequency (GHz)
OIP3, P1dB, Gain and NF Dependence on Vdd at 2GHz, +40C
30
20
10 TOI P1dB 0 4.0 4.3 4.5 4.8 Vdd (V) 5.0 5.3 5.5 Gain NF (x10)
Supply Current, Idd, Variation with Supply Voltage, Vdd
102.5
3.5
3.8
4.0
4.3 Vdd (V)
4.5
4.8
5.0
5.3
5.5
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Preliminary
Caution: ESD Sensitive
Appropriate precaution in handling, packaging and testing devices must be observed.
Pin # 1
Function RF In
Description RF input pin. This pin is at DC ground. An external DC blocking capacitor should be used in most applications. RF output and bias pin. Bias should be supplied to this pin through an external RF choke inductor. Because DC biasing is present on this pin, a DC blocking capacitor should be used in most applications (see application schematic). The supply side of the bias network should be well bypassed. Connection to RF/DC ground. For best performance use via holes as shown in recommended PCB layout to reduce inductance and to provide adequate thermal path.
RF In
2
RF Out/ DC Input
3 Package Backside
GND
Package Dimensions ("43" Ceramic Module)
0.097 (2.47) 0.015 (0.38)
Backside must connect to DC/RF ground
0.272 (6.9)
RF Input
0.394 (10.0)
All dimensions in inches (mm) Denotes Pin 1
Test PCB Pad Layout PCB Front
0.4 (10.16) 0.295 (7.5) 0.275 (6.98) 0.02 (0.51)
0.136 (3.45) 0.024 (0.6)
0.03 (0.76) Solder Outline
0.04 (1.02)
(0.76) 0.028 (0.70) Solder Outline
0.04 (1.02) 0.015 (.38) All plated thru holes: 0.02 (0.5) diameter. All dimensions in inches (mm). Board material: FR-4, 0.032 (.81) thick.
0.05 (1.27) typical
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Part Number Ordering Information
Reel Size 7" 500 Part Number SLX-2143 Devices/Reel
Part Symbolization
The part will be symbolized with an "SLX2143" on the top surface of the package.
Device Schematic
RF Out/ DC In
RF Output/ DC Input
WWYY X-XXXX-X 3412-XLS
.012 (.30) radius
0.03
Package Back PCB Front
0.4 (10.16) 0.295 (7.5) 0.378 (9.6) 0.275 (6.98)
0.024 0.02 (0.51) (0.62)
0.04 0.256 (1.02)
(6.5)
0.04 (1.02) 0.015 0.02 (.50) (.38) 0.05 (1.27) 0.035 (0.90) typical
All dimensions in inches (mm). All plated thru holes: 0.02 (0.5) diameter. All dimensions inCu with Au flash. Material: inches (mm). Board material: FR-4, 0.032 (.81) thick.
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Preliminary
1.7GHz to 2.2GHz Application Schematic
VD C4 C3 L1 C1 RF IN
Package Backside Connect to RF/D C ground
1
SLX-2143
Bill of Materials
Component Designator U1 S1, S2 C1, C2 C3 C4 R1 J1 L1 47 nH 10 pF 220 pF 0.01 uF 0 Value Qty 1 2 2 1 1 1 1 1 SMDI Johnson Components Kemet Kemet Kemet Panasonic Sullins TOKO Vendor Part Number SLX-2143 142-0701-851 C0603C100J5GAC C0603C221J5GAC C0603C103K5RAC POOGCTND S1312-2-ND LL1608-F47NK Description High linearity low noise amplifier SMA side mount connector 0603 capacitor 0603 capacitor 0603 capacitor 0603 jumper 2 pin header 0603 inductor
1.7GHz to 2.2GHz Test Board P/N EEB102508
1.5" (38.1mm)
Sirenza Microdevices LNA
J1 R1 C4 C3 L1 C2 U1 SLX-2143 RF Output S2
VDD
S1 C1 RF Input
1.8" (45.7mm)
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C2
2
RF OUT
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Preliminary
Abstract This application note describes the components and materials that make up the SLX-2143 low noise amplifier module. It also describes the circuit board layout required for optimum performance, and procedures for reliable solder attachment. Introduction The SLX-2143 is a thick film hybrid low noise amplifier designed for 1.7 - 2.2GHz applications that require both low noise figure and good linearity. This module is based on conventional thick film circuit fabrication methods, and can be surface mounted onto circuit boards using industry standard solder reflow techniques. In order to extract peak performance from this amplifier, it is important to use an appropriate circuit board layout, and to ensure that the part is soldered down correctly. Please contact apps@sirenza.com if your application is between 2.2 - 2.5 GHz. Materials The base of the SLX-2143 is an alumina (ceramic) "thick film" substrate, 0.015" (.38mm) thick. The back of this substrate is metallized with plated copper (on a base layer of fired silver) that has been protected with a thin flash of nickel and gold to guarantee solderability, even after extended storage time. The ceramic substrate has via holes that are filled with a fired silver compound. On the component side of the substrate (the side that is covered with the lid) there are conductors based on plated copper (that are protected with a flash of nickel-gold), and pure gold conductors. The copper conductors are formed by plating copper onto a silver conductor that has been fired into the substrate. The fired silver base ensures excellent adhesion to the substrate, and the plated copper ensures that the silver is completely protected. The gold conductors are fired into the substrate and are used wherever wire bonds are required. Thick film resistors are also integrated onto this substrate. A glass passivation layer is used for additional protection, and to act as a solder dam. Inside the module there are several different types of components in use. Solder terminated capacitors and inductors are attached with high temperature lead free (96.5% Sn 3.5% Ag) solder. Chip components are attached with conductive silver epoxy and are connected to the rest
of the circuit with gold wire-bonds. The module is sealed with a ceramic lid that is held down with a B-stage epoxy seal ring. The overall module is non-hermetic, but it will pass a standard "bubble" leak test. The module is designed to be reflowed onto a laminate based circuit board such as FR4. Input and output connections to the module are made with "castellations" on either end of the module. Castellations are rounded metallized notches (metallized with silver, copper, nickel, gold, as in other parts of the module) in the edge of the ceramic substrate. When these are put through a solder reflow process, the solder tends to wick up into the notches, creating a robust solder fillet that can be easily inspected. The third connection, ground, is formed by the rest of the metal on the back of the module.
Board Design As the module has the input, output, and ground connections on the same plane, in principal coplanar waveguide should be used to feed the module. In practice, microstrip can also be used as ground vias under the module connect the "top" ground to a microstrip ground plane. Care still needs to be taken to ensure a graceful transition from microstrip to coplanar waveguide. Care also needs to be taken to ensure that the medium leading up to the module (be it microstrip, coplanar waveguide, or grounded coplanar waveguide) is 50 ohms, with minimal loss. The dimensions used in the evaluation board are recommended (they yield a return loss of 27dB at 2 GHz) if that material structure can be adapted. The evaluation board layout is shown in Figure 1. The DC blocks, bias inductor, and decoupling capacitors are also shown on the board. The coplanar line leading up to the module has a width of 0.04" (1.0mm) with a spacing of 0.02" (0.5mm) to the coplanar ground. The thickness of the board dielectric, FR4, is 0.032" (0.81mm), although typically the overall board thickness is increased with additional layers. One ounce copper is used on both sides. At 2.5GHz, the performance of the FR-4 board material is becoming marginal, so users may find it necessary to adjust the tuning of the part with external turning elements if operating at this frequency. Sirenza Microdevices will provide the detailed layout (in AutoCAD format) to users wishing to use the same layout and materials.
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Preliminary
Figure 1: Evaluation Board Layout
Solder Reflow The module is designed to be soldered onto a pad that has an array of via holes for improved grounding. Note that the module is reasonably tolerant of voids in the solder coverage on the back, but that voids should be avoided because they can result in an increase in thermal impedance, which will result in the module running too hot. The gold content on the back is very small so solder embrittlement will not be a problem. The module can be assembled onto a circuit board using standard oven or IR reflow profiles. It is difficult to recommend any single reflow profile because such profiles depend on the board size, other components on the board, and the reflow equipment in use. The most critical parameter is the peak temperature. Reflow profiles that have a peak temperature on the order of 220C-240C for 30 seconds will be adequate for this part. Lower peak temperatures can be used if the time is increased. For small volume prototype fabrication and rework, a hot plate running at about 250C is recommended, with the part left on only until the solder reflows. Soldering irons are not recommended for mounting or removing the part.
There is a thermal coefficient of expansion mismatch between the module and typical circuit board material, but the small dimensions of the module make the strain induced into the module minimal, so no stress related problems should be encountered. If the module is mounted on a very thin laminate (such as FR-4 0.032" (0.81mm) or less), then care should be taken to avoid flexing the laminate, as the ceramic substrate could crack. This has not been observed on conventional thick circuit board materials. (The evaluation board is a three layer structure with two .032" thick dielectric layers.)
Conclusion The SLX-2143 has been designed to be both easy to use and robust, and lab tests done at Sirenza Microdevices have repeatedly demonstrated this. By following the guidelines in this application note, excellent performance can be achieved. We hope that this application note and the products offered by Sirenza Microdevices will assist you in achieving your design goals. If there are any questions about this module or any other Sirenza Microdevices part, please contact us at apps@sirenza.com.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC 7
el u d o M A N L z H M 0 0 2 2- 0 0 7 1 3 4 1 2- X L S
http://www.sirenza.com EDS-102501 Rev B

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